Memory devices, such as dynamic random access memory (“DRAM”) devices, include at least one array or bank of memory cells arranged in rows and columns. A row of memory cells is normally accessed by decoding a row address and activating a corresponding word line that extends through the array or bank. When a word line is activated, all of the memory cells in the corresponding row are accessed, and that row is said to be “open.” The memory cells in one or more columns of the open row are then accessed by decoding a column address and coupling data bits to or from one or more columns corresponding to the decoded column address.
Opening a row of memory cells normally involves coupling each memory cell in the row to one of a respective pair of complementary digit lines that are provided for each column in the array. Coupling a memory cell to a digit line generates a small differential voltage between the digit lines, which are sensed by a sense amplifier provided for the column. The amount of power consumed in opening a row is largely proportional to the number of memory cells in the row since power is consumed in opening each memory cell. As a result of the large number of memory cells that are typically in each row, opening a row of memory cells can consume a significant amount of power. However, expending the power to open an entire row provides the advantage of allowing faster access times since data to be read from the memory cells in the open row are available by simply coupling data bits from respective columns. It is very common to sequentially read data from or write data to the memory cells in all or most of the columns of a row. Thus, the need to open an entire row at a time usually does not result in any wasted power. However, there are other memory operations in which data are read from only a small number of columns in each row. In such cases, opening an entire row, reading data from or writing data to only a few of the memory cells in that row, and then opening a different row needlessly consumes power. For example, if there are 1024 columns in each row, and data bits are read from only 16 of those columns, the amount of power consumed will be approximately 64 times (i.e., 1024/16) the power that would be used to open a row containing only the 16 memory cells that are read.
Not only does opening an entire row to access only a small number of memory cells in the row unnecessarily consume power, but it can also result in slower operation because an array having a large number of columns results in longer word lines having larger capacitances. The larger capacitance of word lines limit the rate at which voltages on the word lines can change to a level that can activate access transistors used to couple respective memory cells to digit lines.
There is therefore a need for a memory device that limits the number of memory cells that are simultaneously opened when only a relatively few memory cells in the open row will be accessed, thereby limiting the needless consumption of power and needless delay in opening rows of memory cells.